Thin film transistor liquid crystal display (referred to as TFT-LCD) is popular in the market due to its characteristics of small size, low power consumption, no radiation and the like. A metal oxide TFT with the advantages of high mobility, good uniformity, transparency and simple manufacturing process may better meet the development requirement of the TFT-LCD with large size and high refresh rate.
As shown in FIGS. 1 through 3, in the process of manufacturing the metal oxide TFT in the prior art, an etch stop layer is generally added on a metal oxide semiconductor layer to prevent the metal oxide semiconductor layer from being etched when source and drain metal electrodes are etched, so that the metal oxide semiconductor layer is protected from being etched by an etchant for source and drain metals. A design of contact via hole is generally adopted for the etch stop layer. FIG. 1 shows the relationships of position and size between a gate 11 and a semiconductor layer 20 in the prior art, the gate 11 is disposed below the semiconductor layer 20 (a gate insulating layer is disposed between the semiconductor layer 20 and the gate 11 and is not shown in FIG. 1). In a direction (e.g. BB direction in FIG. 1) perpendicular to a gate line 12, the area of the semiconductor layer 20 is smaller than that of the gate 11, and in a direction (e.g. AA direction in FIG. 1) parallel to the gate line 12, the semiconductor layer 20 is flush with the gate 11. FIG. 2 shows the relationships of position and size between a source electrode contact via hole 3 and a drain electrode contact via hole 4 on the semiconductor layer 20 in the prior art, and FIG. 3 is a cross sectional view taken along C-C direction in FIG. 2. As shown in FIG. 2 and FIG. 3, a gate insulating layer 6 (not shown in FIG. 2) is disposed on the gate 11, a semiconductor layer (active layer) 20 is formed on the gate insulating layer 6, and an etch stop layer 5 (not shown in FIG. 2) is deposited on the semiconductor layer 20. The etch stop layer 5 comprises the source electrode contact via hole 3 and the drain electrode contact via hole 4, through which a source electrode and a drain electrode are electrically connected with the active layer 20 respectively.
In the process of implementing the present invention, the inventor discovers that the prior art at least has the following problem: the required precision for alignment is strict, but the precision achieved by the existing process is limited, and in addition, the area of semiconductor layer is smaller than that of the gate. Therefore, when the etch stop layer is etched to form the source electrode contact via hole and the drain electrode contact via hole, the contact via holes may be deviated from positions above the semiconductor layer and positioned above the gate insulating layer where no semiconductor layer exists, and thus the gate insulating layer may be continuously etched during etching, which will lead to a short circuit between the source or drain electrode metal and the gate metal, thereby reducing the product yield.